Hawaii Clocks and Bias

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"DC" BIAS

NAME	FUNCTION	NOMINAL VALUE
VDD	Digital Power	5.0V
VSS	Digital Ground	0.0V
HIGH	Analog High	5.0V
LOW	Analog Low	0.0V
DRAIN	Drain of Output (Source Follower)	0.0V
MUXSUB	Multiplexer Substrate	0.0V
CELLWELL	Cell Nwell Potential	5.0V
DSUB	Detector Substrate	0.0V
VRESET	Detector Reset Voltage	0.5V
CELLDRAIN	Drain of Cell (Source Follower)	0.0V
BIASPOWER	Source of internal pullup for cells	5.0V
BIASGATE	Gate of internal pullup for cells	3.5V
SOURCE	Source of Output (Source Follower)	10K Pullup to 5.0V
BUS	Unbuffered Output	200K pullup to 5.0V

CLOCKS

NAME	FUNCTION	NOMINAL VALUE
LSYNC	Line Sync Clock	0.0 - 5.0V
PIXEL	Pixel Clock	0.0 - 5.0V
FSYNC	Frame Sync Clock	0.0 - 5.0V
LINE	Line Clock	0.0 - 5.0V
RESETB	Reset Enable Clock	0.0 - 5.0V
READ	Read Enable Clock	0.0 - 5.0V

NOTE: All biases should be bypassed with 0.1µF ceramic/metal film capacitors.
Biasgate and Vreset should also have 4.7µF tantalum capacitors in parallel with the 0.1µF ceramic/metal film capacitors.

Email Bill Weissbard (wbweissb@rsc.rockwell.com) with any questions concerning this web page.