1.1. Introduction

The Correlated Double Sampler Board (CDS) takes a differential analogue signal from the CCD pre-amplifier and samples both CCD pixel signal level and CCD output stage reset level. The real signal level is actually the difference between these two values.

The signal is sampled in two stages. First, the CCD is set up to output the reset level. That is the level at the output pin when no charge (due to light on the CCD) is present on that pin. This level is then integrated for a preset time, and the value at the integrator output is stored by a sample and hold circuit. Second, the CCD is clocked to provide the pixel charge output level, that is the level due to light falling on that pixel plus the reset level. Again this value is integrated for a preset time, and the value is stored on another sample and hold circuit.

The two level signal are then fed out onto the backplane where they go to the A/D board. The A/D board subtracts the reset level from the signal level to yield the true pixel value due to light alone.

To prevent over voltage recovery delays, which would otherwise occur, the incoming signal is `clipped' at a preset dc level to prevent linear devices ahead from saturating.

In normal operation the CDS board is controlled by the sequencer board and is synchronised to the CCD readout clocks. For test purposes a dummy signal will be fed to the CDS board inputs. The CDS board output will be monitored with an oscilloscope to verify that the correct signal pattern and level emerges. The control line inputs will be set dynamically by the Test Rig.

1.2. Cleaning Requirements

The board needs to be defluxed.

1.3. Equipment

1. CDS Board Test Card
2. Dual Trace Oscilloscope with differential input capability

The CDS board is tested in the process of setting it up.

1. Set the 21 links on the CDS board to be the same as the following diagram.

Figure 1. CDS Jumper Link Positions

1. Check that R/C modifications are on the back of the board as shown below. The wires should be covered with heat shrink.

Figure 2. CDS R/C Modifications on Underside of Board.

1. With power off insert the CDS board into the chassis. Insert the CDS test card into the rack. Ensure that the CDS test card is linked to the CDS card with the 10 way ribbon cable. Power up the chassis with the tested boards as shown in the diagram below.
   

Figure 3. Chassis Contents for CDS Testing.

1. Set Clipping level: The CDS test card is linked to the CDS board. (Input signal from test card causes TP1 to swing beyond the required clipping point). Start the CDS routine going by typing CONT-PIX o

Figure 4. Clipping Waveform Diagram

1. Set the Test Select switch on the CDS board Test card to position 1. Monitor TP2 with the scope. Adjust P3 so that the positive clipping level is +6V  0.1V. Adjust P4 so that the negative clipping level is -3V  0.1V.
2. DC common mode adjustment: Set the DC test mode going by typing DC-TEST o
3. Ensure input pins are shorted together by selecting position 2 for the test card switch.
4. Monitor both the CDS board outputs with the scope in differential mode. Adjust P2 so that minimum difference is achieved. The minimun value will be dependent on the offset set by P5 later. To pass this test the value < 0.19 Volts.
5. AC common mode adjustment: Set the AC test mode going by typing AC-TEST o .
6. Ensure the input pins are shorted by selecting the test select switch to position 2.
7. Monitor both the CDS board outputs with the scope in differential mode. Adjust P1 so that minimum difference is achieved. The minimun value is again dependent on the offset set by P5 later. To pass the test the value < 0.14 Volts.
8. Offset adjustment: Set the CDS into continuous running by typing DC-TEST o
9. The inputs are shorted together and tied to ground, the differential output should be set to give 10 mV  1 mV by adjusting P5. (This is equivalent to 100 ADU's with a 10 ADU range if it were converted by the ADC card).
10. Range detector adjustment: This feature has not been used in practice so it is not necessary to adjust the range detector.

A scope trace from a probe placed on TP2, with the test routine CONT-PIX executing will have the wave shape as shown in figure 4. The limits of excursion will be +6V  0.1V maximum and -3V  0.1V minimum.

The AC and DC common mode adjustments should be adjusted to give minimun values. The AC bias common mode < 0.14 Volts and the DC bias common mode < 0.19 Volts.

The offset when CDS is operated with the test routine DC-TEST executing the differential output of the card should be 10 mV  1 mV.

RGO reserves the right to refuse units of unacceptable quality.

The above test procedure shall be used to determine whether the module is functionally acceptable.