The coplanarity and relative positions of the two chips was measured using the RGO flatness scanner. Each chip was flat to within the resolution of the flatness scanner, which in this case was about 5mm.

Chip butting was done with the aid of 50mm PTFE shims that were removed after the chips were securely bolted to the base plate. The gap between active Silicon on either side of the join is approximately 39 pixels.