0 ( DEFINE CLOCKS ) SEQUENCER DEFINITIONS DECIMAL ( smt 27 Jul 98)
1 ( *** EEV42 CCD *** 2 CHIP MOSAIC *** O/P Left CHANNEL A *** )
2 9600 BAUD \ Baud rate for engineer's terminal
3 00 0 CLOCK TRACKA ( TS0 ) 01 1 CLOCK ADC1 ( AC0 )
4 02 0 CLOCK SIG-SAMPA ( CS0 ) 03 0 CLOCK REF-SAMPA ( CR0 )
5 04 1 CLOCK SIG-RSTA ( RS0 ) 11 1 CLOCK REF-RSTA ( RR0 )
6 17 1 CLOCK CLAMPA ( CL0 ) 25 0 CLOCK RSCKA ( RSA )
7 ( HA1) 23 1 CLOCK 1HCKA \ Stored here as well - see VCLK
8 ( HA2) 30 0 CLOCK 2HCKA ( wrap board A - labelled H3 )
9 ( HA3) 34 0 CLOCK 3HCKA ( wrap board A - labelled H2 )
10 ( HA4) 28 0 CLOCK SWCKA
11 ( VA1) 24 0 CLOCK 1VCKA \ Store charge at V2
12 ( VA2) 26 1 CLOCK 2VCKA ( wrap board A - labelled V3 )
13 ( VA3) 19 0 CLOCK 3VCKA ( wrap board A - labelled V2 )
14 ( VA4) 31 0 CLOCK 4VCKA
15 ( VLA) 35 1 CLOCK RD/IA --> \ V+ DF, V++ ND
 

2 RAM-DISK 0

0 ( DEFINE CLOCKS ) SEQUENCER DEFINITIONS DECIMAL ( smt 20 Oct 98)
1 ( *** EEV42 CCD *** 2 CHIP MOSAIC *** O/P Left CHANNEL B *** )
2
3 07 0 CLOCK TRACKB ( TS1 ) 08 1 CLOCK ADC2 ( AC1 )
4 05 0 CLOCK SIG-SAMPB ( CS1 ) 10 0 CLOCK REF-SAMPB ( CR1 )
5 13 1 CLOCK SIG-RSTB ( RS1 ) 15 1 CLOCK REF-RSTB ( TR1 )
6 12 1 CLOCK CLAMPB ( CL1 ) 32 0 CLOCK RSCKB ( RSB )
7 ( HB1) 21 1 CLOCK 1HCKB \ Stored here as well - see V
8 ( HB2) 27 0 CLOCK 2HCKB ( wrap board A - labelled H3 )
9 ( HB3) 14 0 CLOCK 3HCKB ( wrap board A - labelled H2 )
10 ( HB4) 16 0 CLOCK SWCKB
11 ( VB1) 22 0 CLOCK 1VCKB
12 ( VB2) 36 1 CLOCK 2VCKB ( wrap board A - labelled V3 )
13 ( VB3) 20 0 CLOCK 3VCKB ( wrap board A - labelled V2 )
14 ( VB4) 29 0 CLOCK 4VCKB
15 ( VLB) 33 1 CLOCK RD/IB --> \ V+ DF, V++ ND

 
3 RAM-DISK 0

0 ( Horizontal clock ) SEQUENCER ( smt 20 Oct 98)
1 0 SOR HCLOCK
2 RSCKA 10 DF 20 ND
3 1HCKA 5 DF 15 ND
4 2HCKA 15 ND
5 3HCKA 10 DF 15 ND
6 SWCKA 10 DF 15 ND
7 RSCKB 10 DF 20 ND
8 1HCKB 5 DF 15 ND
9 2HCKB 15 ND
10 3HCKB 10 DF 15 ND
11 SWCKB 10 DF 15 ND
12 35 EOR
13 HCLOCK >RAM
14 \ Routine used for clearing and windowing.
15 -->

4 RAM-DISK 0

0 ( Idle routine ) SEQUENCER ( smt 12 Nov 98)
1 1 SOR HRINT \ Removes serial register spillage
2
3 RSCKA 25 ND RSCKB 25 ND
4 1HCKA 5 DF 15 ND 1HCKB 5 DF 15 ND
5 2HCKA 15 ND 2HCKB 15 ND
6 3HCKA 10 DF 15 ND 3HCKB 10 DF 15 ND
7 \ 4VCKA 1000 ND 4VCKB 1000 ND
8
9 1005 EOR HRINT >RAM
10
11
12
13
14
15 -->

 
5 RAM-DISK 0

0 ( Vertical clock ) SEQUENCER ( smt 12 Nov 98)
1
2 3 SOR VCLOCK \ RD/IA 100 ND
3 \ RD/IB 100 ND
4 1VCKA 300 DF 300 ND
5 2VCKA 200 DF 300 ND
6 3VCKA 100 DF 300 ND
7
8 1VCKB 300 DF 300 ND
9 2VCKB 200 DF 300 ND
10 3VCKB 100 DF 300 ND
11
12 3HCKA 950 ND 3HCKB 950 ND
13 1002 EOR
14 VCLOCK >RAM
15 -->

 
6 RAM-DISK 0

0 ( Loading binned pixels smt 12 Oct 98)
1 ( The next blocks hold the waveform changes for binned pixels )
2 ( It require the X binning factor on the stack when loaded.)
3
4 ( This block holds parameters used to locate the required block)
5
6
7 \ binning factors 2,3,4,8 only
8
9 BLK @ 1+ VHT BIN-BLOCK !
10 4 SOR BIN
11 3 FH LOAD
12
13 \ The BINNING routine only operates at the STANDARD readout
14 \ speed, even if the CCDC has been set to another speed.
15
 

7 RAM-DISK 0

0 ( X BINNING TURBO SPEED 4+4 us CDS) DECIMAL ( smt 12 Oct 98)
1 SEQUENCER VIA SEQUENCER FORTH ENDVIA DEFINITIONS
2 : COMPILE-BIN-PIX ( xbin-factor - ) >R BIN SOR
3 RSCKA 15 ND
4 CLAMPA 5 DF I 25 * DF 5 DF 125 ND
5 1HCKA 5 DF I 0 DO 5 DF 15 ND 5 DF LOOP
6 2HCKA 5 ND I 0 DO 15 ND 10 DF LOOP
7 3HCKA 5 DF I 0 DO 5 DF 15 ND 5 DF LOOP
8 SWCKA 5 DF I 25 * ND 55 ND 10 DF 65 ND
9 REF-SAMPA 5 DF I 25 * DF 5 DF 40 ND
10 SIG-SAMPA 5 DF I 25 * DF 80 DF 40 ND
11 SIG-RSTA 5 DF I 25 * DF 5 DF 125 ND
12 REF-RSTA 5 DF I 25 * DF 5 DF 125 ND
13 TRACKA 5 DF I 25 * DF 80 DF 45 ND
14 ADC1 5 DF I 25 * DF 125 DF 5 ND
15 [ -->

 
8 RAM-DISK 0

0 ( X BINNING TURBO SPEED 4+4 us CDS) DECIMAL ( smt 12 Oct 98)
1 ] ( needed since routine requires 2 ram-disk blocks )
2 RSCKB 15 ND
3 CLAMPB 5 DF I 25 * DF 5 DF 125 ND
4 1HCKB 5 DF I 0 DO 5 DF 15 ND 5 DF LOOP
5 2HCKB 5 ND I 0 DO 15 ND 10 DF LOOP
6 3HCKB 5 DF I 0 DO 5 DF 15 ND 5 DF LOOP
7 SWCKB 5 DF I 25 * ND 55 ND 10 DF 65 ND
8 REF-SAMPB 5 DF I 25 * DF 5 DF 40 ND
9 SIG-SAMPB 5 DF I 25 * DF 80 DF 40 ND
10 SIG-RSTB 5 DF I 25 * DF 5 DF 125 ND
11 REF-RSTB 5 DF I 25 * DF 5 DF 125 ND
12 TRACKB 5 DF I 25 * DF 80 DF 45 ND
13 ADC2 5 DF I 25 * DF 125 DF 5 ND
14 R> 25 * 135 + EOR BIN >RAM ;
15 COMPILE-BIN-PIX BIN-TEMP FORGET COMPILE-BIN-PIX

 
9 RAM-DISK 0

0 ( STANDARD SPEED 8+8 us CDS ) CR SEQUENCER ( smt 06 Nov 98)
1 12 SOR SP0
2 RSCKA 13 ND RSCKB 13 ND
3 CLAMPA 25 DF 220 ND CLAMPB 25 DF 220 ND
4 1HCKA 5 DF 15 ND 1HCKB 5 DF 15 ND
5 2HCKA 15 ND 2HCKB 15 ND
6 3HCKA 5 DF 15 ND 3HCKB 5 DF 15 ND
7 SWCKA 5 DF 125 ND 10 DF 105 ND
8 SWCKB 5 DF 125 ND 10 DF 105 ND
9 REF-SAMPA 35 DF 80 ND REF-SAMPB 35 DF 80 ND
10 SIG-SAMPA 150 DF 80 ND SIG-SAMPB 150 DF 80 ND
11 SIG-RSTA 25 DF 220 ND SIG-RSTB 25 DF 220 ND
12 REF-RSTA 25 DF 220 ND REF-RSTB 25 DF 220 ND
13 TRACKA 150 DF 85 ND TRACKB 150 DF 85 ND
14 ADC1 240 DF 5 ND ADC2 240 DF 5 ND
15 246 EOR SP0 >RAM -->

 
10 RAM-DISK 0

0 ( QUICK speed 6 + 6us CDS ) SEQUENCER ( smt 22 Oct 98)
1 7 SOR SP1
2 RSCKA 13 ND RSCKB 13 ND
3 CLAMPA 25 DF 180 ND CLAMPB 25 DF 180 ND
4 1HCKA 5 DF 15 ND 1HCKB 5 DF 15 ND
5 2HCKA 15 ND 2HCKB 15 ND
6 3HCKA 5 DF 15 ND 3HCKB 5 DF 15 ND
7 SWCKA 5 DF 95 ND 10 DF 95 ND
8 SWCKB 5 DF 95 ND 10 DF 95 ND
9 REF-SAMPA 35 DF 60 ND REF-SAMPB 35 DF 60 ND
10 SIG-SAMPA 125 DF 60 ND SIG-SAMPB 125 DF 60 ND
11 SIG-RSTA 25 DF 180 ND SIG-RSTB 25 DF 180 ND
12 REF-RSTA 25 DF 180 ND REF-RSTB 25 DF 180 ND
13 TRACKA 125 DF 65 ND TRACKB 125 DF 65 ND
14 ADC1 200 DF 5 ND ADC2 200 DF 5 ND
15 206 EOR SP1 >RAM -->

 
11 RAM-DISK 0

0 ( TURBO SPEED 4 + 4 us CDS ) SEQUENCER ( smt 06 Nov 98)
1 8 SOR SP2
2 RSCKA 13 ND RSCKB 13 ND
3 CLAMPA 23 DF 135 ND CLAMPB 23 DF 135 ND
4 1HCKA 5 DF 15 ND 1HCKB 5 DF 15 ND
5 2HCKA 15 ND 2HCKB 15 ND
6 3HCKA 5 DF 15 ND 3HCKB 5 DF 15 ND
7 SWCKA 5 DF 68 ND 10 DF 75 ND
8 SWCKB 5 DF 68 ND 10 DF 75 ND
9 REF-SAMPA 30 DF 40 ND REF-SAMPB 30 DF 40 ND
10 SIG-SAMPA 98 DF 40 ND SIG-SAMPB 98 DF 40 ND
11 SIG-RSTA 23 DF 135 ND SIG-RSTB 23 DF 135 ND
12 REF-RSTA 23 DF 135 ND REF-RSTB 23 DF 135 ND
13 TRACKA 98 DF 45 ND TRACKB 98 DF 45 ND
14 ADC1 153 DF 5 ND ADC2 153 DF 5 ND
15 159 EOR SP2 >RAM -->

 
12 RAM-DISK 0

0 ( NONASTRO SPEED 3 + 3 us ) SEQUENCER ( smt 06 Nov 98)
1 2 SOR SP3
2 RSCKA 13 ND RSCKB 13 ND
3 1HCKA 5 DF 15 ND 1HCKB 5 DF 15 ND
4 2HCKA 15 ND 2HCKB 15 ND
5 3HCKA 5 DF 15 ND 3HCKB 5 DF 15 ND
6 REF-SAMPA 25 DF 30 ND REF-SAMPB 25 DF 30 ND
7 SIG-SAMPA 83 DF 30 ND SIG-SAMPB 83 DF 30 ND
8 SWCKA 5 DF 60 ND 8 DF 53 ND
9 SWCKB 5 DF 60 ND 8 DF 53 ND
10 TRACKA 83 DF 35 ND TRACKB 83 DF 35 ND
11 ADC1 123 DF 4 ND ADC2 123 DF 4 ND
12 CLAMPA 25 DF 100 ND CLAMPB 25 DF 100 ND
13 SIG-RSTA 25 DF 100 ND SIG-RSTB 25 DF 100 ND
14 REF-RSTA 25 DF 100 ND REF-RSTB 25 DF 100 ND
15 138 EOR SP3 >RAM -->
 

13 RAM-DISK 0

0 ( FLASH Clear of CCD ) SEQUENCER ( smt 12 Nov 98)
1 9 SOR FLASH-CLR
2 \ RD/IA 350 ND RD/IB 350 ND
3 1VCKA 150 DF 150 ND 1VCKB 150 DF 150 ND
4 2VCKA 100 DF 150 ND 2VCKB 100 DF 150 ND
5 3VCKA 50 DF 150 ND 3VCKB 50 DF 150 ND
6 \ 4VCKA 400 ND 4VCKB 400 ND
7 RSCKA 400 ND RSCKB 400 ND
8 1HCKA 400 DF 1HCKB 400 DF
9 2HCKA 400 ND 2HCKB 400 ND
10 3HCKA 400 ND 3HCKB 400 ND
11 SWCKA 400 ND SWCKB 400 ND
12 402 EOR FLASH-CLR >RAM
13
14
15 -->

 
14 RAM-DISK 0

0 ( DUMMY PIXEL ROUTINE 1+1us CDS) SEQUENCER ( smt 06 Nov 98)
1 10 SOR DUMMY-PIXEL
2 RSCKA 13 ND RSCKB 13 ND
3 CLAMPA 15 DF 59 ND CLAMPB 15 DF 59 ND
4 1HCKA 4 DF 10 ND 1HCKB 4 DF 10 ND
5 2HCKA 9 ND 2HCKB 9 ND
6 3HCKA 4 DF 10 ND 3HCKB 4 DF 10 ND
7 SWCKA 5 DF 26 ND 8 DF 35 ND
8 SWCKB 5 DF 26 ND 8 DF 35 ND
9 REF-SAMPA 18 DF 10 ND REF-SAMPB 18 DF 10 ND
10 SIG-SAMPA 44 DF 10 ND SIG-SAMPB 44 DF 10 ND
11 SIG-RSTA 15 DF 59 ND SIG-RSTB 15 DF 59 ND
12 REF-RSTA 15 DF 59 ND REF-RSTB 15 DF 59 ND
13
14
15 185 EOR DUMMY-PIXEL >RAM -->

 
15 RAM-DISK 0

0 ( Very Fast Clear of CCD-NOT USED) SEQUENCER ( smt 12 Nov 98)
1 11 SOR QUICK-CLR
2
3 1VCKA 150 DF 150 ND 1VCKB 150 DF 150 ND
4 2VCKA 100 DF 150 ND 2VCKB 100 DF 150 ND
5 3VCKA 50 DF 150 ND 3VCKB 50 DF 150 ND
6 4VCKA 400 ND 4VCKB 400 ND
7 RSCKA 400 ND RSCKB 400 ND
8 1HCKA 400 DF 1HCKB 400 DF
9 2HCKA 400 ND 2HCKB 400 ND
10 3HCKA 400 ND 3HCKB 400 ND
11 SWCKA 400 ND SWCKB 400 ND
12 402 EOR QUICK-CLR >RAM
13 \ Actually does a V clock triplet and at the same time sets the
14 \ serial register all high. RUN 2 X NO. OF ROWS
15 -->

 
16 RAM-DISK 0

0 \ ( IDLE+IMO routine ) SEQUENCER ( 06 Nov 93)
1 \ --> 12 SOR ABM-CLK
2 \ RD/IA 32000 ND RD/IB 32000 ND
3 \ RSCKA 32000 ND SWCKA 32000 ND
4 \ 1HCKA 32000 ND 1HCKB 32000 ND
5 \ 2HCKA 32000 DF 2HCKB 32000 DF
6 \ 3HCKA 32000 ND 3HCKB 32000 ND
7 \ RSCKB 32000 ND SWCKB 32000 ND
8 \ 1VCKA 4000 DF 8000 ND 1VCKB 4000 DF 8000 ND
9 \ 2VCKA 6000 DF 4000 ND 2VCKB 6000 DF 4000 ND
10 \ 3VCKA 32000 DF 3VCKB 32000 DF
11 \ 4VCKA 32000 ND 4VCKB 32000 DF
12 \ 30002 EOR ABM-CLK >RAM --> \ MAX LENGTH
13 \ ROUTINE PREVENTS COLUMN BLOOMING FROM SATURATED STAR.
14 \ V++ SWITCHED TO V+ WHICH IS OPTIMISED FOR EACH CCD
15 -->

 
17 RAM-DISK 0

0 ( SETUP FUNCTIONS. smt 12 Nov 98)
1 SP0 SET-SPEED0 \ Standard speed function
2 SP1 SET-SPEED1 \ Quick speed
3 SP2 SET-SPEED2 \ turbo
4 SP3 SET-SPEED3 \ nonastro
5 SP0 SET-SPEED4 \ NOT USED WAS CCD1 ONLY
6 BIN SET-BIN \ Binning function
7 DUMMY-PIXEL SET-DPIX \ Dummy pixel routine
8 HCLOCK SET-HCLK \ H clock
9 VCLOCK SET-VCLK \ V clock
10 HRINT SET-HIDLE \ IDLE ONLY
11
12
13
14 QUICK-CLR SET-QCLR
15 FLASH-CLR SET-FCLR --> \ FLASH CLEAR

 
18 RAM-DISK 0

0 ( Customisations for 2 CHIP CAMERA ) ( smt 06 Nov 98)
1 1P 2 1 I-OFFSET ! 99 1 OD-ZERO ! \ IS,OD Offset = Ch. 1
2 1P 3 2 I-OFFSET ! 99 2 OD-ZERO ! \ Ch. 2
3
4
5 1P 2016 'ZERO-AD ! 30 'SERVO-ZERO ! \ 1unit=-0.16degC
6 C1(ABG) SEQ-BREG CLR-BIT \ 2 CH. FOR ABG TGUP
7 98 YEAR W! NETWORK CCD1 40 PREFLASH-SCALER !
8 ( ************************************************************ )
9 1V 2148 4128 13 NEW-TYPE EEV48 EEV48 \ CCD TYPE
10 ( *********** DO NOT EDIT LINE 9 OF THIS BLOCK ************** )
11 : HOPG 2 OPG ; : LOPG 1 OPG ;
12
13 50 QUICK-VCLKS/LINE ! \ 40 '#CLR-VCLK ! \ New CLEAR algorithm
14 FORTH DEFINITIONS PAGE ." TWO CHIP MOSAIC CAMERA " 500 MS
15 : ENBT 1 'SILENT W! VT100 RAM-DISK 1 LIST ; I'M smt -->
 
 
 

Chip 0 Configuration.

Virtual head number 1

Serial number is :- EEV 7461-14-6 (CCD 1)

0 0.00 Volts Channel 0
1 0.00 Volts Channel 0
2 0.00 Volts Channel 0
3 0.00 Volts Channel 0
4 0.00 Volts Channel 0
5 0.00 Volts Channel 0
6 0.00 Volts Channel 0
7 0.00 Volts Channel 0
V+S0 -17.70 Volts Channel 8
V-0 -16.00 Volts Channel 9
V+0 -4.00 Volts Channel 10
V-SL 2.40 Volts Channel 11
RD0 2.50 Volts Channel 12
VSS0 -6.00 Volts Channel 13
OG -14.00 Volts Channel 14
V++0 -4.00 Volts Channel 15
R-S0 2.00 Volts Channel 16
R-0 -13.00 Volts Channel 17
R+0 -4.00 Volts Channel 18
R+S0 -18.00 Volts Channel 19
ODL0 7.00 Volts Channel 20
ODH0 16.20 Volts Channel 21
OGH -13.00 Volts Channel 22
OGL 3.00 Volts Channel 23
N/C1 0.00 Volts Channel 24
BG 7.00 Volts Channel 25
DUMP 6.00 Volts Channel 26
H++0 -4.00 Volts Channel 27
H+0 -4.00 Volts Channel 28
H- -14.50 Volts Channel 29
H-S0 2.00 Volts Channel 30
H+S0 -18.00 Volts Channel 31
<CCD1> ok
>

  Chip 1 Configuration.

Virtual head number 1

Serial number is :- EEV 7461-11-6 (CCD 2)

0 0.00 Volts Channel 0
1 0.00 Volts Channel 0
2 0.00 Volts Channel 0
3 0.00 Volts Channel 0
4 0.00 Volts Channel 0
5 0.00 Volts Channel 0
6 0.00 Volts Channel 0
7 0.00 Volts Channel 0
V+S1 -17.70 Volts Channel 40
V-1 -16.00 Volts Channel 41
V+1 -4.00 Volts Channel 42
V-S1 2.40 Volts Channel 43
RD1 2.25 Volts Channel 44
VSS1 -6.00 Volts Channel 56
N/C2 0.00 Volts Channel 46
V++1 -4.00 Volts Channel 47
R-S1 2.00 Volts Channel 48
R-1 -13.00 Volts Channel 49
R+1 -4.00 Volts Channel 50
R+S1 -18.00 Volts Channel 51
ODL1 7.00 Volts Channel 52
ODH1 16.30 Volts Channel 53
N/C3 0.00 Volts Channel 54
N/C6 0.00 Volts Channel 55
N/C4 0.00 Volts Channel 45
N/C7 0.00 Volts Channel 57
N/C5 0.00 Volts Channel 58
H++1 -4.00 Volts Channel 59
H+1 -4.00 Volts Channel 60
H-1 -14.50 Volts Channel 61
H-S1 2.00 Volts Channel 62
H+S1 -18.00 Volts Channel 63
<CCD1> ok
>