When characterised using the Dutch controller, the mosaic chips had common Substrate, OG1 and OG2 connections. All the other connections were independently driven using separate clock boards for the two chips. Cross talk between the chips was just visible on frames containing bright extended sources, but cross sections across these ghosts revealed that they had sub-ADU amplitude.
The operating voltages were measured at the pre-amp using a DVM and were identical for both CCDs.
Image Area clocks :
Serial Register clocks:
Lo - 14.6V
Hi - 3.5V
OG2 Lo-gain +3V
OG2 Hi-gain -12V
Dump Drain +6V
The output FET Drain current was set to 2mA.
These potentials were recommended by EEV and are very close to the device maximums. The OD and Image Area clock lo potentials are very critical. The Dump Gate is treated as another vertical phase and is driven using the same potentials as for the Image Area clocks. When referring to EEV data sheets, note that all potentials are quoted relative to image area clock lo.