DESCRIPTION OF THE CCD CLOCK BOARDs
The clock board contains two 'virtual boards' : board 2 and board 3. The convention at ING is to use the board 2 clocks to control the CCD Serial clocks and the board 3 clocks to control the CCD Parallel clocks. The table below shows the address of each clock and which clock number routes to which connector pin. Writing 1's or 0's to the relevant address selects Clock-Hi or Clock-Lo respectively.
SDSU Clock Board Connector |
|
|
|
Pin number on 37 Way D connector |
Clock Name (SDSU convention) |
(serial) Board 2 addresses |
(parallel) Board 3 addresses |
1 |
CLK 0 |
1 |
|
2 |
CLK 1 |
2 |
|
3 |
CLK 2 |
4 |
|
4 |
CLK 3 |
8 |
|
5 |
CLK 4 |
$10 |
|
6 |
CLK 5 |
$20 |
|
7 |
CLK 6 |
$40 |
|
8 |
CLK 7 |
$80 |
|
9 |
CLK 8 |
$100 |
|
10 |
CLK 9 |
$200 |
|
11 |
CLK 10 |
$400 |
|
12 |
CLK 11 |
$800 |
|
13 |
CLK 12 |
|
1 |
14 |
CLK 13 |
|
2 |
15 |
CLK 14 |
|
4 |
16 |
CLK 15 |
|
8 |
17 |
CLK 16 |
|
$10 |
18 |
CLK 17 |
|
$20 |
19 |
CLK 18 |
|
$40 |
24 |
GND |
|
|
25 |
GND |
|
|
33 |
CLK19 |
$80 |
|
34 |
CLK20 |
$100 |
|
35 |
CLK21 |
$200 |
|
36 |
CLK22 |
$400 |
|
37 |
CLK23 |
$800 |
The clock-hi and clock-lo voltage levels are controlled by writing to the DACs present on the clock board. These DACs are controlled by writing a 24 bit word to virtual clock board 2. These words have the following formats :
To program the +ve voltage level of clock number n :
(CLK2<<8)+(2n<<14)+$XXX
To program the -ve voltage level of clock number n :
(CLK2<<8)+((2n+1)<<14)+$XXX
In these examples $XXX is the hex value written to the target DAC. $000 corresponds to -10V, $FFF to +10V (Smaller DAC ranges are resistor programmable using R70 of the clock board).
Updated awr 9 July 2013